1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and, more particularly, to an asynchronous pseudo SRAM which uses a DRAM (Dynamic Random Access Memory) or ferroelectric memory in the memory core portion.
2. Description of the Related Art
Pseudo SRAMs are commercially available, which use a DRAM or ferroelectric memory in the memory core portion to increase the degree of integration while maintaining use compatibility to existing SRAMs. The mainstream of conventional pseudo SRAMs is a synchronous type which controls the operations of internal circuits by a clock signal (internal circuit control signal) time-serially generated in the device from an external input signal, e.g., an external chip enable signal /CE, as shown in FIGS. 1A and 1B.
In recent years, a demand for pseudo SRAMs oriented for cellular phones is increasing. Especially, a demand for asynchronous pseudo SRAMs which operate even asynchronously to an external input signal is growing.
To implement an asynchronous pseudo SRAM, an operation as shown in the timing charts of FIGS. 2A and 2B is necessary. FIG. 2A shows a read operation. FIG. 2B shows a write operation. To realize the read and write operations shown in FIGS. 2A and 2B, for example, an arrangement shown in FIG. 3 can be used. More specifically, a plurality of address transition detection circuits (row/column system ATDs 100) which detect address transition are prepared. A row address signal ADx output from a row address buffer circuit 101 and a column address signal ADy output from a column address buffer circuit 102 are supplied to the row/column system ATD 100, thereby detecting the transition of row and column addresses. On the basis of an AND signal ATDSUM of the detection result by the row/column system ATD 100, an internal CE control circuit 103 generates an internal chip enable signal (internal circuit control signal) INCE to control the internal circuits. The internal chip enable signal INCE is supplied to a row system circuit 104 and column system circuit 105. Signals that time-serially drive a word line WL and plate line PL in a memory cell array 106 are generated to control the data read and write (Dout and Din) operations.
In this arrangement, the cycle time defined by the external input signals (external chip enable signal /CE and address signals ADx and ADy) can freely be set. However, the internal chip enable signal INCE used to control the operations of the internal circuits has a predetermined cycle time because the signal is generated by using a timeout circuit (with constant time).
A proposal has been made in which the above-described restriction on the write operation should be eliminated by executing read and write operations as shown in the timing charts of FIGS. 4A and 4B. More specifically, in the read operation, the internal chip enable signal INCE (auto pulse) is generated by using a timeout circuit, as shown in FIG. 4A. In the write operation, the operations of the internal circuits are controlled by an external write enable signal /WE, as shown in FIG. 4B, without using any timeout circuit.
Additionally, asynchronous pseudo SRAMs often have a high-speed operation mode such as a static column mode in which the memory cells of a row selected by a row address are sequentially accessed by a column address signal, as shown in FIG. 1B.
However, the conventional pseudo SRAM cannot execute the high-speed operation mode such as a static column mode while operating asynchronously to an external input signal. This is because an asynchronous pseudo SRAM cannot discriminate between row access that is triggered by the transition of row and column addresses and column access that is also triggered by the transition of a column address. In addition, since the asynchronous pseudo SRAM controls the operations of the internal circuits by using a timeout circuit, the cycle time of the internal circuits is constant. That is, the arrangement is not compatible to a special operation mode.
Hence, there is a demand for implementation of a semiconductor integrated circuit device which can operate a pseudo SRAM asynchronously to an external input signal and also asynchronously execute a high-speed operation mode.
To meet this demand, for example, Jpn. Pat. Appln. KOKAI Publication No. 2002-269977 discloses the following arrangement. Two ATDs for row access and column access are prepared. In addition, a mode determination circuit is arranged, which generates an internal circuit control signal having a desired length necessary for access on the basis of the ATDs and determines two modes. The mode is automatically determined on the basis of the interval of address transition.
In the arrangement disclosed in this prior art, however, the address transition interval detection time must be set within a predetermined range. The cycle time of the column access mode cannot freely be set.